View PACDN006_124013.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CALIFORNIA MICRO DEVICES
PACDN006
6 Channel ESD Protection Array
Features
* Six channels of ESD protection * 15KV ESD protection (HBM) * 8KV contact, 15KV air ESD protection per IEC 1000-4-2 * Low loading capacitance, 3pF typ. * Miniature 8-pin MSOP or SOIC package
Applications
* I/O port protection for cellular phones, notebook computers, PDAs, etc. * ESD protection for VGA (Video) port in PC's or Notebook computers * ESD protection for sensitive electronic equipment.
Product Description
The PACDN006 is a diode array designed to provide 6 channels of ESD protection for electronic components or sub-systems. Each channel consists of a pair of diodes which steers the ESD current pulse either to the positive (VP) or negative (VN) supply. The PACDN006 will protect against ESD pulses up to 15 KV Human Body Model (100 pF capacitor discharging through a 1.5K resistor) and 8KV contact discharge per International Standard IEC1000-4-2. This device is particularly well-suited for portable electronics (e.g. cellular phones, PDAs, notebook computers) because of its small package footprint, high ESD protection level, and low loading capacitance. It is also suitable for protecting video output lines and I/O ports in computers and peripheral equipment.
SCHEMATIC CONFIGURATION
S TA N D A R D PA R T O R D E R I N G I N F O R M AT I O N
Package Pins 8 8 Style SOIC MSOP Ordering Part Number Part Marking PDN006S D006
When placing an order please specify desired shipping: Tubes or Tape & Reel.
(c)2000 California Micro Devices Corp. All rights reserved. All rights reserved. PAC DN006TM is a tradmark of California Micro Devices Corp. 6/19/2000
C0970500
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
1
CALIFORNIA MICRO DEVICES
PACDN006
A B S O L U T E M A X I M U M R AT I N G S
Diode Forward DC Current (Note 1) Storage Temperature Operating Temperature Range DC Voltage at any Channel Input 20mA -65C to 150C -20C to 85C VN -0.5V to VP + 0.5V
S TA N D A R D S P E C I F I C AT I O N S
Parameter Operating Supply Voltage (VP - VN ) Supply Current, (VP - VN ) = 5.5V, T = 25C Diode forward Voltage, IF = 20mA, T = 25C ESD Protection Peak Discharge Voltage at any Channel Input, in-system (Note 2) Human Body Mode., Method 3015 (Note 3, 4) Contact Discharge per IEC 1000-4-2 (Note 5) Channel Clamp Voltage @ 15KV ESD HBM, T = 25C (Note 3, 4) Positve trnsients Negative transients Channel Leakage Current, T = 25C Channel Input Capacitance (Measured @ 1MHz) VP = 5V, VN = 0V, VIN P U T = 2.5V (Note 4) Package Power Rating SOIC Package MSOP Package
Note Note Note Note 2: From I/O pins to VP or VN only. VP bypassed to VN with 0.2 mF ceramic capacitor. 3: Human Body Model per MIL-STD-883, Method 3015, CDischarge=100pF, RDischarge=1.5K, VP=5.0V, VN=GND. 4: This parameter is guaranteed by design and characterization. 5: Standard IEC1000-4-2 with CDischarge=150pF, and RDischarge=330, VP=5V, VN=GND.
Min.
Typ.
Max. 5.5V 10A
0.65V
0.95V T
15KV 8KV
0.1A 3pF
VP + 13.0V VN - 13.0V 0.1A 6pF 350mW 200mW
Input Capacitance vs. Input Voltage
5
Input Capacitance (pF)
4 3 2 1 0 0 1 2 3 4 5
Input Voltage
Typical variation of CIN with VIN (VP = 5V, VN = 0V, 0.1F chip capacitor between VP & VN)
(c)2000 California Micro Devices Corp. All rights reserved. All rights reserved. PAC DN006TM is a tradmark of California Micro Devices Corp.
2
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
6/19/2000
CALIFORNIA MICRO DEVICES
Application Information
See also California Micro Devices Application note AP209, "Design Considerations for ESD protection." In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of a positive ESD pulse applied between an input channel and Chassis Ground. The parasitic series inductance back to the power supply is represented by L1. The voltage VZ on the line being protected is: VZ = Forward voltage drop of D1 + L1 x d(IESD)/ dt + VSUPPLY where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC 61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1nS. Here d(IESD)/dt can be approximated by DIESD/Dt, or 30/(1x10-9). So just 10nH of series inductance (L1) will lead to a 300V increment in VZ! Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased negative voltage on the line being protected. Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit a much higher output impedance to
PACDN006
fast transient current spikes. In the VZ equation above, the VSUPPLY term, in reality, is given by (VDC + IESD x ROUT), where VDC and ROUT are the nominal supply DC output voltage and effective output impedance of the power supply respectively. As an example, a ROUT of 1 ohm would result in a 10V increment in VZ for a peak IESD of 10A. To mitigate these effects, a high frequency bypass capacitor should be connected between the VP pin of the ESD Protection Array and the ground plane. The value of this bypass capacitor should be chosen such that it will absorb the charge transferred by the ESD pulse with minimal change in VP. Typically a value in the 0.1F to 0.2F range is adequate for IEC-61000-4-2 level 4 contact discharge protection (8KV). For higher ESD voltages, the bypass capacitor should be increased accordingly. Ceramic chip capacitors mounted with short printed circuit board traces are good choices for this application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. For extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply voltage. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply and ground planes to minimize stray series inductance.
Figure 1.
(c)2000 California Micro Devices Corp. All rights reserved. All rights reserved. PAC DN006TM is a tradmark of California Micro Devices Corp. 6/19/2000
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3

▲Up To Search▲

Price & Availability of PACDN006

	To Download PACDN006 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .